Method and apparatus for digital to analog conversion with minimized distortion
US5321401A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 4, 1992 |
| Grant date | Jun 14, 1994 |
| Priority date | — |
| Expiry date | Dec 4, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/785
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital to analog converter (10) and method is provided in which a plurality of digital to analog converter cells (16) generate an analog output signal based on a digital input signal, the cells being characterized by a switching threshold. An error signal circuit (22) generates a control voltage signal for controlling a first variable delay register (12). Signals latched by the first variable delay register (12) are characterized by rising and falling edges, and the first variable delay register (12) is controlled by the control voltage signal such that the rising and falling edges cross the switching threshold at substantially the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.