Multiple slope analog-to-digital converter
US5321403A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1993 |
| Grant date | Jun 14, 1994 |
| Priority date | — |
| Expiry date | Apr 14, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/52
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiple slope integrating analog-to-digital converter (ADC) includes many improvements and refinements which eliminate timing and non-linearity errors which accumulate due to a large number of switching operations that occur over an integrate cycle. The ADC includes an integrator and a comparator in which an input voltage to be measured is applied to a summing node at the input of the integrator during an integrate cycle, while at the same time positive and negative reference currents are selectively applied to the summing node by a controller which monitors the output of the comparator in order to limit the voltage magnitude at the output of the integrator. Thereafter, during a de-integrate cycle, the input voltage is disconnected while progressively shallower ramps are measured with a high-speed clock for greater resolution and accuracy. The comparator has a slight hysteresis built in to slightly separate the switching thresholds for positive-going and negative going ramps. The switches which control selection of the positive and negative reference currents are implemented in such a way that current surges are minimized. A method is provided to control the order in which the s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.