Dual-scale topology optoelectronic matrix algebraic processing system
US5321639A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1992 |
| Grant date | Jun 14, 1994 |
| Priority date | — |
| Expiry date | Mar 2, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06E1/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel architecture matrix algebraic processing system exhibits patterns of arrayed (i) light transmitters and (ii) light receivers that are identical, but at differing scales. Planar arrays of one or more optoelectronic processors--principally semiconductor chips or chip arrays--having both computational and light input/output capabilities optically communicate from one plane to the next through free-space space-invariant optical data distributions--principally lenses and computer-generated holograms--having both replication and distribution capabilities. Each optoelectronic processor, or OP, consists of a number of arrayed optoelectronic processing elements, or OPEs. The OPEs, in turn, typically consist of a number of optoelectronic sub-processing units are preferably electrically interconnected in a tree-based structure, preferably an H-tree. Leaf units include typically one light detector plus local memory, logic circuitry, and electrical input/output. Fanning units typically include local memory, logic circuitry, and electrical input/output. A root unit typically includes electrically-connected local memory, logic circuitry, electrical input/output, and a light transmitter…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.