Interference suppression system
US5321724A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1992 |
| Grant date | Jun 14, 1994 |
| Priority date | — |
| Expiry date | Oct 23, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/30
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A line driver is coupled by a pair of signal lines to a receiver. Preprocessing circuitry, for processing signals arriving on the pair of signal lines at the receiver, includes regulating circuitry for regulating the voltage between the signal lines between predetetermined limits and thereby modifying the sensitivity of the system to compensate for changes in line conditions and reject interference when the line driver is powered down. The regulating means includes: bias circuitry, for putting a bias on the signal passing through to the receiver, so as to hold the receiver input away from the triggering voltage level so that it is not triggered by noise; and bias limiting circuitry, responsive to signals from the driver so as to limit or reduce the effective bias, so that the sensitivity of the system to true signals from the driver is not reduced below a desired level. A resistor is connected between the two signal lines. A current regulating circuit includes circuitry for feeding a current through the resistor; and, for each signal line, there is current adjustment circuitry, responsive to the conditions on the signal lines for adjusting the current passing through the correspond…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.