Virtual memory management method and apparatus utilizing separate and independent segmentation and paging mechanism
US5321836A · kind A · utility
78Cited by
81References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 9, 1990 |
| Grant date | Jun 14, 1994 |
| Priority date | — |
| Expiry date | Apr 9, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Microprocessor architecture for an address translation unit which provides two levels of memory management is described. Segmentation registers and an associated segmentation table in main memory provide a first level of memory management which includes attribute bits used for protection, priority, etc. A page cache memory and an associated page directory and page table in main memory provide a second level of management with independent protection on a page level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.