Improved method of fabricating antifuses in an integrated circuit device and resulting structure
US5322812A · kind A · utility
66Cited by
9References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1991 |
| Grant date | Jun 21, 1994 |
| Priority date | — |
| Expiry date | Oct 24, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/935
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various improvements in the fabrication of an antifuse having silicon-amorphous silicon-metal layer structure are presented. Included are improved deposition techniques for the amorphous silicon layer. The improvements include steps for the fabrication of such an antifuse without the use of platinum and the resulting antifuse and contact structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.