Semiconductor device including integrated injection logic and vertical NPN and PNP transistors
US5323054A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1992 |
| Grant date | Jun 21, 1994 |
| Priority date | — |
| Expiry date | Jul 1, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/673
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same substrate, grooves that reach an n.sup.+ -type buried layer 5 serving as an emitter of the IIL and an n.sup.+ -type buried layer 4 serving as a collector of the vertical npn transistor are formed at the same time, and an oxide film 101 is formed only on the sidewall of each groove; in the grooves, n.sup.+ -type polycrystalline silicon films 103 and 102 are formed, which are made to serve as an emitter lead-out portion of the IIL and a collector wall of the vertical npn transistor, respectively; a p-type diffused layer 17 serving as an injector of the IIL and a p-type diffused layer 18 and p.sup.- -type diffused layer 12 serving as the base thereof are respectively so formed as to be adjoining to the oxide film 101 of the emitter lead-out portion of the IIL; and a p-type diffused layer 16 serving as the base of the vertical npn transistor is so formed as to be adjoining to the oxide film 101 of the collecter wall. The semiconductor device can achieve a smaller cell size, a decrease in parasitic capacitance and an increase in operating speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.