Direct I/O access to express bussing in a configurable logic array
US5323069A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 18, 1993 |
| Grant date | Jun 21, 1994 |
| Priority date | — |
| Expiry date | Jun 18, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a generally rectangular matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical rows of logic cells. The array further includes at least one horizontally aligned express bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned express bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array further includes a plurality of logic cell I/O pins located at the periphery of the matrix and connectable to the logic cells in the rows and columns at the periphery of the matrix. Furthermore, the array includes a plurality of express bus I/O pins directly connectable to the express busses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.