Semiconductor memory device having multiple memory arrays and including redundancy circuit for repairing a faulty bit
US5323348A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1991 |
| Grant date | Jun 21, 1994 |
| Priority date | — |
| Expiry date | Sep 30, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Column repairing circuits 7a, 7b for repairing a DRAM in which there are defective memory cells in two columns are disclosed. The connection state of switching elements or circuits 51-5n, 61-6n, 71-7 (n+1), 81-8 (n+1) is determined as illustrated by appropriately disconnecting fuses in fuse links provided respectively in circuits 7a, 7b. Accordingly, column selecting lines Y2a and Y (n+1) b in memory array blocks 891a, 891b are not activated. The two repairing circuits 7a, 7b are provided spaced apart from each other on a semiconductor substrate, so that excessive concentration of fuse elements and switching elements or circuits is prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.