Circuitry for regenerating digital signals in extended distance communications systems
US5323420A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 26, 1991 |
| Grant date | Jun 21, 1994 |
| Priority date | — |
| Expiry date | Jul 26, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/023
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A regeneration circuit (16) is disclosed for regenerating noisy, received digital signals in a high impedance signal line (22). A buffer amplifier (30) is provided with a feedback resistor (36), with the feedback resistor and input to the buffer amplifier coupled to line (22) and to a pull-up resistor (34). The values of resistors (34 and 36) are selected such that when a normally "high" logic potential on line (22) is pulled "low" and then released, the buffer amplifier functions to source current to line (22) during the falling transition; and after the amplifier transitions "low," it sinks current from line (22). Thus, buffer amplifier (30) acts first as a pull-up device during the falling transition and then as a pull-down device during the rising transition. This restores the received logic signals to digital levels and reduces noise about the switching points in the rising and falling transitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.