Method of fabricating an electronic interconnection
US5324892A · kind A · utility
43Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1992 |
| Grant date | Jun 28, 1994 |
| Priority date | — |
| Expiry date | Aug 7, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of fabricating an electronic interconnection structure comprising at least one solder column Joined to an I/O pad of a substrate, the method including the steps of: PA1 (a) applying a quantity of solder to the solder column or I/O pad; PA1 (b) aligning the solder column with the I/O pad such that there is a quantity of solder between them; PA1 (c) heating the structure to cause the solder to melt and bond the column to the I/O pad; and PA1 (d) planarizing the solder column to a predetermined height. Also disclosed is the electronic interconnection structure made by the method according to the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.