High-breakdown voltage field-effect transistor
US5324969A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1992 |
| Grant date | Jun 28, 1994 |
| Priority date | — |
| Expiry date | Aug 12, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/221
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field-effect transistor including a first channel layer, formed in contacting relationship with a gate electrode, and a second channel layer, formed on one side or both sides of the first channel layer in non-contacting relationship with the gate electrode, the carrier concentration in the second channel layer being higher than that in the first channel layer but lower than that in high-impurity concentration active layers forming drain and source regions. The field-effect transistor employs an offset gate configuration in which the gate electrode is formed in contacting relationship with the first channel layer at a position nearer to the high-impurity concentration active layer forming the source region than to the high-impurity concentration active layer forming the drain region. A dummy gate is formed and ion implantation is performed from two different angles using the dummy gate as a mask, thereby efficiently forming the source region, drain region, and second channel layer in a sequence of successive processing steps. By combining the suitably patterned first and second ion shielding layers, the gate to source electrode spacing and the gate to drain electrode spacing are c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.