Neuron unit and neuron unit network
US5324991A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1992 |
| Grant date | Jun 28, 1994 |
| Priority date | — |
| Expiry date | Dec 11, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A neuron unit processes a plurality of binary input signals and outputs a neuron output signal which is indicative of a result of the processing. The neuron unit is provided with a plurality of first gates respectively for carrying out a logical operation on a binary input signal and a weighting coefficient, a second gate for carrying out a logical operation on an excitatory output signal of each of the first gates, a third gate for carrying out a logic operation on an inhibitory output signal of each of the first gates, a fourth gate for synthesizing output signals of the second and third gates and outputting the neuron output signal, and a generating circuit for generating the weighting coefficients which are supplied to each of the first gates. The generating circuit for generating one weighting coefficient includes a random number generator for generating random numbers, and a comparator for comparing each random number r with a predetermined value q and for outputting a pulse signal having first and second values depending on whether each random number r is such that r.ltoreq.q or r>q, and each weighting coefficient is described by a pulse density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.