Method and apparatus for non-atomic level parity protection for storing data in a random access memory
US5325375A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 1991 |
| Grant date | Jun 28, 1994 |
| Priority date | — |
| Expiry date | Jun 28, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1056
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method and apparatus provides a parity bit for every m multiples of b bits, a group of b bits being the smallest number of bits that can be manipulated by the CPU. The parity bit is computed for the entire m x b bits during a write operation, even if only a subset of the m multiples of b bits is being stored. The write operation is implemented as a read-modify-write operation of the entire m x b bits, with parity error reporting suppressed for the read portion of the operation. However, the parity bit is set factoring in whether a parity error is detected during the read portion of the operation. The parity bit for the entire m x b bits is checked during a read operation, even if only a subset of the m multiples of b bits is needed. Any detected parity error is reported to the CPU. As a result, hardware cost is substantially reduced with minimal degradation to data integrity. Furthermore, the method and apparatus is completely transparent to the CPU and the operating system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.