Selectable pointer validation in a computer system
US5325496A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 1991 |
| Grant date | Jun 28, 1994 |
| Priority date | — |
| Expiry date | Dec 24, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system is described having selectable pointer validation. The pointer structure is modified to provide selectable pointer validation. Each pointer comprises an effective address portion and a validation enable field. The effective address portion defines the memory location referenced by the pointer. The validation enable field comprises one or more bits of information that indicate whether or not selectable pointer validation is enabled for the particular pointer. Prior to executing a pointer reference, a processor first loads the desired condition of the validation enable field of the pointer. In normal practice of the invention, a programmer would enable selective pointer validation for particular pointers under debug testing or pointers for which a problem may have been encountered. For those pointers for which selective pointer validation is disabled, the pointer reference to the specified effective address occurs without any pointer validation processing. If, however, selective pointer validation is enabled by setting the appropriate value in the validation enable field, additional processing steps are performed by the present invention in order to validate the acc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.