Processor that performs memory access in parallel with cache access
US5325508A · kind A · utility
41Cited by
23References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 1993 |
| Grant date | Jun 28, 1994 |
| Priority date | — |
| Expiry date | May 7, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes an accessible memory controller, an accessible cache controller, and circuitry for accessing the accessible memory controller and the accessible cache controller simultaneously. Certain preferred embodiments of the present invention also include a deassertable miss line, that is, a line which when deasserted indicates that the data was found in the cache and that the memory access should be cancelled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.