Single-component memory controller utilizing asynchronous state machines
US5325515A · kind A · utility
1Cited by
5References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 14, 1991 |
| Grant date | Jun 28, 1994 |
| Priority date | — |
| Expiry date | May 14, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asynchronous memory controller comprises plurality of flip-flops connected in a series. The input of the first flip-flop receives a signal indicating the start of a bus cycle. The input of each succeeding flip-flop in the series is connected to the output of the preceding flip-flop. The odd-numbered flip-flops in the series are activated by a first state of a clock pulse; the even-numbered flip-flops in the series are activated by a second state of a clock pulse. Each flip-flop responds to a level of the clock pulse rather than a rising or falling edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.