Processor system with dual clock
US5325516A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1992 |
| Grant date | Jun 28, 1994 |
| Priority date | — |
| Expiry date | Mar 9, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i.e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i.e. the address status signal) generated by the CPU. The ADS and RDY signals must be modified in a first way if the CPU calls for a memory cycle at the beginning of a bus cycle and i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.