Linking microprocessor interrupts arranged by processing requirements into separate queues into one interrupt processing routine for execution as one routine
US5325536A · kind A · utility
32Cited by
10References
6Claims
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Key dates
| Filing date | Nov 24, 1992 |
| Grant date | Jun 28, 1994 |
| Priority date | — |
| Expiry date | Nov 24, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiple interrupt request data is stored in a queue and handled by a single interrupt sub-routine to provide a batch handling capability to maximize the interrupt handling efficiency of a microprocessor. Events are organized into groups having a common interrupt handling requirement and a data storage queue is provided for each group. At least one data word is stored for each event requiring interrupt attention in a respective queue. An interrupt handling routine upon a single call handles all data words within a queue before exiting the interrupt handling routine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.