Semiconductor static RAM having thin film transistor gate connection

US5327003A · kind A · utility

Assignee

• FUJITSU LIMITED · JP

Inventors

• Kazuo Itabashi · Kawasaki, JP
• Taiji Ema · Inabe, JP

Key dates

• Filing date: Jan 15, 1993
• Grant date: Jul 5, 1994
• Expiry date: Jan 15, 2013

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/903

Abstract

A semiconductor memory device includes a semiconductor substrate, a memory cell provided on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, where each of the first and second transfer transistors, the first and second driver transistors and the first and second thin film transistor loads have a source, a drain and a gate electrode, and a connecting region in which the drain of the second thin film transistor load, the gate electrode of the first thin film transistor load and the gate electrode of the first driver transistor are connected. The gate electrode of the first driver transistor, the gate electrode of the first thin film transistor load and the drain of the second thin film transistor load are made of conductor layers which are stacked on the semiconductor substrate with an insulator layer interposed between the conductor layers, and a top one of the stacked conductor layers makes contact with a top surface of a bottom one of the stacked conductor layers and with side surfaces of each conductor layer provided between the top and bottom conductor layers with…