Distortion-free limiter for a power amplifier
US5327101A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1993 |
| Grant date | Jul 5, 1994 |
| Priority date | — |
| Expiry date | Jul 2, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G11/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A distortion limiter for limiting the amount of distortion of an inverting amplifier is disclosed. A comparator produces a pulse when a signal level at an inverting input of the inverting amplifier exceeds a reference voltage level. The pulse charges a capacitor. When the charge on the capacitor is sufficient to raise the gate voltage of a junction field-effect transistor (FET) above cutoff, the FET shunts the input signal to reduce its level. The distortion characteristics can be controlled by using a voltage divider to adjust the voltage across the FET. A bias voltage at the gate of the FET, keeps the FET turned off when the inverting amplifier is not clipping.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.