Semiconductor memory device
US5327372A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 1993 |
| Grant date | Jul 5, 1994 |
| Priority date | — |
| Expiry date | Jan 14, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/652
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CAM cell array for storing a logical address is divided into first to third CAM sections. A first partition switch circuit intervenes between a zeroth piece of sense line connected to a sense circuit and a first piece of sense line for the first CAM section. The sense circuit is a circuit for selecting a RAM cell array in which a physical address to be read out is stored. A second partition switch circuit intervenes between the first piece of sense line and a second piece of sense line for the second CAM section. A third partition switch circuit intervenes between the second piece of sense line and a third piece of sense line for the third CAM section. By controlling switching operation of respective partition switch circuits according to page size, optimum length of the sense line is utilized, thus achieving a high-speed address translation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.