Method of making high voltage PNP bipolar transistor in CMOS
US5328859A · kind A · utility
14Cited by
1References
2Claims
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Key dates
| Filing date | Jan 4, 1993 |
| Grant date | Jul 12, 1994 |
| Priority date | — |
| Expiry date | Jan 4, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/011
Abstract
A high voltage bipolar transistor fabricated on a CMOS substrate without adding any additional process steps. During the CMOS n-well mask and implant steps an n-well is formed for the transistor. Next, during the CMOS field and deep boron implant steps a circular p-field is formed within the n-well. Finally, during the CMOS p+ mask and implant steps the p+ emitter is formed. The presence of the p-field between the emitter and n+ base provides high voltage protection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.