Multiple biasing phase-lock-loops controlling center frequency of phase-lock-loop clock recovery circuit
US5329251A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 1993 |
| Grant date | Jul 12, 1994 |
| Priority date | — |
| Expiry date | Apr 28, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1258
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A recovered clock signal is phase aligned with timing data that has been extracted by a digital signal processor (DSP) from an input signal by a multiple phase-lock-loop (PLL) clock recovery circuit that utilizes a digital error word generated by the DSP. The multiple PLL clock recovery circuit uses a first PLL and a second PLL to generate a first biasing signal and a second biasing signal, respectively, which have a magnitude which is a function of the frequency of a first clock signal and a second clock signal, respectively. A multiplexor allows either the first biasing signal or the second biasing signal to be selected as a selected bias signal. A controlled oscillator generates the recovered clock signal with a center frequency which is a function of the magnitude of a phase error signal. A digital-to-analog converter (DAC) generates the phase error signal by modifying the selected bias signal in response to the digital error word. The first biasing signal and the second biasing signal can be switched in and out of the DAC to quickly bias the DAC to drive the controlled oscillator to a specific center frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.