Synthetic aperture radar digital signal processor
US5329283A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 1993 |
| Grant date | Jul 12, 1994 |
| Priority date | — |
| Expiry date | Apr 28, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01S13/9004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A digital signal processor optimized for synthetic aperture radar image formation provides two separate stages of arithmetic processing along independent in-phase and quadrature channels. The first stage accepts a first reference input and integrates a multiplier/accumulator for each channel, and the second stage accepts a second reference input and includes a multiplier and an adder for each channel. In addition to hardware to select and route data in accordance with a desired operation, a hold register is incorporated prior to input-selection logic to facilitate complex-by-complex multiplications of data derived from either input in the first stage. Hold registers are also included before the second-stage adders to permit a complex multiplication with magnitude weighting to occur during the zero-th stage of a fast Fourier transformation, effectively hiding the time to perform one FFT stage. A control section contains a microprogrammed control sequencer, an input/output controller, data address generators and two reference address generators, the data and address generators being implemented using digital differential analyzers, or DDAs, which may be combined to form second-order …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.