Semiconductor device having a memory cell
US5329481A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1992 |
| Grant date | Jul 12, 1994 |
| Priority date | — |
| Expiry date | Dec 14, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device with at least one programmable memory cell which includes a bipolar transistor (T.sub.1) with an emitter (11) and a collector (12) of a first conductivity type and a base (10) of a second, opposite conductivity type. The emitter (11) and collector (12) are coupled to a first supply line (100) and a second supply line (200), respectively. The base (10) is coupled to writing means (WRITE) through a control transistor (T.sub.2). Reading means (READ) are included in a current path (I) which extends between the first supply line (100) and the second supply line (200) and which includes a current path between the emitter (11) and collector (12). In a preferred embodiment, the collector (12) is in addition coupled to the second supply line (200) via a switchable load (T.sub.5).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.