DRAM having exclusively enabled column buffer blocks
US5329489A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 1992 |
| Grant date | Jul 12, 1994 |
| Priority date | — |
| Expiry date | Mar 13, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A random access array memory device which uses a static buffer as a cache for speeding the access times achievable for data retrieval from the device. The static buffer is operationally divided into two or more blocks so that each block holds a block of data from a different row of the array. The division of a single buffer into several operational blocks significantly increases the "hit" probability of the cache, allowing fast access from the buffer. A control system stores the row address (TAG) of each of the multiple blocks and compares that address to the row address of the data desired and signals the result of that comparison. Random access memory arrays of the multiple line cache configuration are employed in data processing systems including a CPU, address and data buses, control logic, and multiplexers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.