Integrated semiconductor memory array and method for operating the same

US5329493A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Willibald Meyer · Hersbruck, DE
• Norbert Wirth · Unterschleißheim, DE

Key dates

• Filing date: Jun 9, 1993
• Grant date: Jul 12, 1994
• Expiry date: Jun 9, 2013

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C7/103
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated semiconductor memory array includes a memory region, a writing buffer memory associated with the memory region, a writing pointer and an input buffer associated with the writing buffer memory, a reading buffer memory associated with the memory region, a reading pointer and an output buffer associated with the reading buffer memory, and a control device being formed of a memory control circuit and a data flow control circuit. A reading column address decoder controlling the reading pointer is associated with the reading buffer memory. A reading address control unit is connected to the reading column address decoder, and a reading address register is connected to the reading address control unit. A writing column address decoder controlling the writing pointer is associated with the writing buffer memory. A writing address control unit is connected to the writing column address decoder, and a writing address register is connected to the writing address control unit. A line address decoder is provided in the memory control circuit or in the memory region and is triggerable by the reading address control unit and the writing address control unit.