Decimation filter for a sigma-delta converter and data circuit terminating equipment including the same
US5329553A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 1992 |
| Grant date | Jul 12, 1994 |
| Priority date | — |
| Expiry date | May 4, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0664
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decimation filter for converting a received train of sigma-delta pulses in synchronism with a sigma-delta clock (fs) into a train of Pulse Code Modulation (PCM) samples having a PCM clock in accordance with the formula ##EQU1## includes a computer for computing one PCM sample from a sequence of sigma-delta samples in synchronism with the PCM clock and also a comparison circuit for determining whether phase correction of the PCM clock is necessary to lock the generation of the PCM samples on the sigma-delta clock extracted from the received sigma-delta signal, the decimation filter including shifters which shift the computation process at least one sigma-delta clock pulse in order to provide phase control in the generation of the PCM samples.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.