Microprocessor which optimizes bus utilization based upon bus speed
US5329621A · kind A · utility
8Cited by
8References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1989 |
| Grant date | Jul 12, 1994 |
| Priority date | — |
| Expiry date | Oct 23, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus having a bus speed counter for determining the bus speed of a previous bus cycle. This previous bus speed information is then used to optimize bus utilization. This bus speed information is particularly useful for determining whether to run prefetch bus cycles during the execution of a conditional branch instruction. If previous bus cycles have been slow, prefetch procrastination can occurs until the branch condition resolves.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.