Method and apparatus for a translation lookaside buffer with built-in replacement scheme in a computer system
US5329627A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1992 |
| Grant date | Jul 12, 1994 |
| Priority date | — |
| Expiry date | Apr 17, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/121
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for selecting an entry to be replaced in a translation lookaside buffer in a computer system. The translation lookaside buffer stores a plurality of entries of virtual-to-physical address translations with each entry having a used bit and a valid bit. The circuit comprises a validity circuit coupled to the valid bit of each entry for determining whether the entry is valid and if not, the validity circuit causes a first signal to be asserted; a use circuit coupled to the used bit of each entry and to the validity circuit for determining whether the entry is used when a control signal is present and if not, the use circuit asserts a second signal to the validity circuit, the asserted second signal causing the first signal to be asserted; a ripple circuit coupled to each entry, its previous entry and its next entry, the ripple circuit receiving the first signal from the validity circuit of each entry and a first FOUND signal from its previous entry, the ripple circuit outputting a second FOUND signal, the ripple circuit causing the second FOUND signal to be asserted when the first signal is asserted and the first FOUND signal is de-asserted, the ripple circuit c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.