Method for making a MOS device

US5330925A · kind A · utility

Assignee

• AT&T Bell Laboratories · US

Inventors

• Kwing F. Lee · Red Bank, US
• Ran-Hong Yan · Leyland, GB

Key dates

• Filing date: Jun 18, 1992
• Grant date: Jul 19, 1994
• Expiry date: Jun 18, 2012

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

A method for manufacturing an MOS device, such as a PMOS transistor, on a silicon wafer. The method includes steps leading to the formation of a polysilicon gate electrode, and at least one ion-implantation step for forming source and drain junction regions in the silicon wafer. The method further comprises, before the ion-implantation step, the step of forming a first sidewall contactingly disposed adjacent the polysilicon gate electrode. The ion-implantation step is then performed such that the resulting source and drain junction regions are at least partially excluded from that portion of the silicon wafer that directly underlies the polysilicon gate electrode and the sidewall. In preferred embodiments of the invention, a first ion-implantation step is performed after the first sidewall is formed, then a second sidewall is formed adjacent and contiguous with the first sidewall, and then a second ion-implantation step is performed, resulting in the formation of further source and drain junction regions which are at least partially excluded from that portion of the silicon wafer that directly underlies the polysilicon gate electrode and the first and second sidewalls.