Method for fabricating semiconductor circuits
US5330933A · kind A · utility
8Cited by
9References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 10, 1992 |
| Grant date | Jul 19, 1994 |
| Priority date | — |
| Expiry date | Jul 10, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/15
Abstract
A method for fabricating a resistive load element for a semiconductor device can be used with standard semiconductor processes. A layer of second level poly is deposited and lightly doped P-type. A resist mask is used to dope selected regions of the poly layer N-type. The poly layer is then patterned to define conductors and resistive load elements. The resistive load elements are formed by back-to-back PN diodes formed at the interfaces between the P-type and N-type regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.