Integrated circuit package in which impendance between signal pads and signal lines is matched by reducing the size of a ground plane
US5331204A · kind A · utility
24Cited by
3References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1992 |
| Grant date | Jul 19, 1994 |
| Priority date | — |
| Expiry date | Oct 19, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An object of the present invention is to match impedance of each portion of whole lines of a signal wiring with the integrated circuit mounted on the package. All ground planes are deleted within a region vertically under/above a connection pad provided on the top- or bottom-surface of a polyimide multilayer part, whereby no capacitance is generated between the connection pad and the ground planes, so that the impedance of the signal wiring within the region right under/above the connection pad is prevented from being lowered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.