Self-testing logic with embedded arrays
US5331643A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 4, 1991 |
| Grant date | Jul 19, 1994 |
| Priority date | — |
| Expiry date | Sep 4, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318558
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Shift register latch scan strings employed in level sensitive scan design methodology for built-in circuit self-test are provided with bypassable portions which are made to serve effectively as address registers for arrays which are embedded in blocks of logic for which the scan strings are meant to provide pseudo-random excitation test data. Additionally, the bypassable portion of the scan strings is connected to an address stepper mechanism which insures complete coverage throughout the range of cell addresses within the array. This is accomplished through the utilization of a stepping counter or the utilization of an linear feedback shift register or similar mechanism. It thus becomes possible to insure that every cell address in the array is provided with known pseudo-random data at the beginning of a test and which is also capable of readily providing array cell content information at the end of the test and/or at various times during test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.