Transmission gate
US5332916A · kind A · utility
22Cited by
2References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1992 |
| Grant date | Jul 26, 1994 |
| Priority date | — |
| Expiry date | Sep 28, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transmission gate having a CMOS structure wherein an NMOS transistor and a PMOS transistor are connected in parallel between an input signal line and an output signal line and a separation layer which separates a transistor formation region for one of the PMOS transistor and the NMOS transistor formed in a substrate from the substrate, wherein the back gates of the respective transistors are constituted to receive an input signal from the input signal line when the one transistor and the other transistor formed in a well region are in a conductive state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.