Built-in fault testing of integrated circuits
US5332973A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1992 |
| Grant date | Jul 26, 1994 |
| Priority date | — |
| Expiry date | May 1, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Built-in current mode quiescent current monitoring circuitry is provided for measuring a circuit's or a subcircuit's quiescent current. Anomalously high quiescent current (Iddq) generally results as a consequence of a manufacturing defect. These defects include those not detected by tests generated using traditional fault models. The technique provided here is based upon generating a proportionally matched current to the circuit under test current by a control loop. The proportionally matched current is then sent to a comparator where it is compared to a reference current, the reference current representing an acceptable quiescent current level. The output of the comparator then indicates whether the quiescent current is above or below the reference current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.