Active matrix flat display
US5333004A · kind A · utility
16Cited by
4References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1991 |
| Grant date | Jul 26, 1994 |
| Priority date | — |
| Expiry date | Nov 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0219
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
This invention concerns active matrix flat displays in which the pixels (10) are placed at the intersections between two mutually-perpendicular sets of conductors known as lines (L1 to LN) and columns (C1 to CM). In the invention, each pixel consists of two capacitors (CON1, CON'1) connected in series and consisting of electro-optical components, this circuit being connected between two control transistors (T1, T'1), these two transistors being connected to a common line (L1) and two different columns (C1, C'1) respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.