Multilayer ceramic chip capacitor
US5335139A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 1993 |
| Grant date | Aug 2, 1994 |
| Priority date | — |
| Expiry date | Jul 13, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/435
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multilayer ceramic chip capacitor includes alternately stacked dielectric layers and internal electrode layers. The dielectric layers contain barium titanate as a major component and magnesium oxide, manganese oxide, barium oxide and/or calcium oxide, silicon oxide and optionally, yttrium oxide as minor components in such a proportion that there are present 0.1-3 mol of MgO, 0.05-1.0 mol of MnO, 2-12 mol of BaO+CaO, 2-12 mol of SiO.sub.2 and up to 1 mol of Y.sub.2 O.sub.3 per 100 mol of BaTiO.sub.3. The capacitor satisfies the standard temperature dependence of capacitance and shows a minimized change of capacitance with time under an applied DC electric field and a long insulation resistance life. Where the dielectric layers contain 0.1-3 mol of MgO, 1-5 mol of Y.sub.2 O.sub.3, 2-12 mol of BaO+CaO, and 2-12 mol of SiO.sub.2 per 100 mol of BaTiO.sub.3, the capacitor shows improved DC bias performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.