Error correction code pipeline for interleaved memory system
US5335234A · kind A · utility
14Cited by
18References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 1993 |
| Grant date | Aug 2, 1994 |
| Priority date | — |
| Expiry date | May 7, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data stream process pipeline and method of transferring data from a storage device to a central processor unit (CPU) or cache memory includes an input latch arrangement, error correcting circuitry, and an output latch arrangement. In embodiments of the present invention the input and output latch arrangements include two latches and means for multiplexing the outputs of the two latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.