Shift register system for driving active matrix display
US5335254A · kind A · utility
8Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1993 |
| Grant date | Aug 2, 1994 |
| Priority date | — |
| Expiry date | Apr 27, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A clock control circuit for sequentially enabling the clock input terminal of a number of groups of shift register stages for reducing the power consumption. The groups are seccessively activated, and the groups currently not in operation are made not to consume power. During changeover between adjacent groups of shift register stages, the clocks for the different groups overlap to insure stable operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.