Information processing apparatus with optimization programming
US5335330A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 13, 1991 |
| Grant date | Aug 2, 1994 |
| Priority date | — |
| Expiry date | May 13, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processing apparatus wherein a plurality of instructions are checked in an instruction buffer circuit, the plurality of instructions excluding instructions being executed. If there are instructions which can be executed simultaneously, then the instructions are converted to one instruction and executed. By adjusting the value of a program counter so that new instructions at subsequent addresses can be supplied to the buffers left empty by the above conversion, instructions which require multiple cycles to execute can be processed in one cycle. Using one selector control signal, the necessary number of instructions can be supplied from the instruction cache and executed continuously without leaving the instruction buffer empty after multiple instructions are converted to one instruction and executed. Load instructions which do not need to be executed repeatedly in a program containing loops can be canceled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.