Byte-swap hardware simulator for a sixteen bit microprocessor coupled to an eight bit peripheral unit
US5335340A · kind A · utility
7Cited by
5References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 29, 1992 |
| Grant date | Aug 2, 1994 |
| Priority date | — |
| Expiry date | May 29, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arrangement for enabling a sixteen bit microprocessor to transfer data to and from a peripheral unit operating in an eight bit mode includes a single OR gate for simulating an odd address so that only the low byte portion of the data bus is utilized. A subroutine in the microprocessor causes the microprocessor to act as if all addresses in the peripheral unit are even and to force the OR gate to an active state whenever the real address in the peripheral unit is odd.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.