On-wafer integrated circuit electrical testing
US5336992A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1992 |
| Grant date | Aug 9, 1994 |
| Priority date | — |
| Expiry date | Jun 3, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/07357
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An electrical testing device is provided for testing integrated circuits located on a wafer. The testing device employs a multi-layer test circuit having a plurality of contacts for contacting the integrated circuits on a wafer. The layers of the test circuit are embedded in a flexible, supportive dielectric material which allows vertical flexing of the contacts. Cross bar switches are further employed to switch among the plurality of contacts thereby enabling the testing of individual dies of the water to be tested. A microprocessor is further included for controlling the switching and the testing of each die. In an alternate embodiment, the plurality of contacts are mechanically moved relative to the wafer to allow testing of the dies without the need for the switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.