Pulse density modulation circuit (parallel to serial) comparing in a nonsequential bit order
US5337338A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 1993 |
| Grant date | Aug 9, 1994 |
| Priority date | — |
| Expiry date | Feb 1, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M5/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pulse density modulation circuit has a counter which produces a most significant bit through a least significant bit output based on a clock input. The circuit also has a comparator with two sets of most significant bit through least significant bit inputs that produces an output based on a comparison of the two sets of inputs. The first set of comparator most significant bit through least significant bit inputs receives respectively a most significant bit through a least significant bit of an input reference signal. The second set of comparator most significant bit through least significant bit inputs receives the counter most significant bit through least significant bit output in a non-sequential bit order. The non-sequential bit order can be a bit reversed order wherein the counter most significant bit through least significant bit output are respectively connected to the comparator least significant bit through most significant bit input. The circuit may further filter the comparator output to provide a resultant analog output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.