Application specific exclusive of based logic module architecture for FPGAs
US5338983A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 1993 |
| Grant date | Aug 16, 1994 |
| Priority date | — |
| Expiry date | Dec 10, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic module (20) includes five input terminals (a-e), two output terminals (F1, F2), and control logic (22, 24, 26, 28, 30, 32, 36) for selectively coupling one or more of the input terminals to one of the output terminals. First and second input terminals (a, b) are connected to inputs of a first XOR gate (22); a third input terminal (c) is connected to one input of a multiplexor (24) through an inverter (26); a fourth input terminal (d) is connected to the other input of the multiplexor (24) and to one input of a first NAND gate (28); and a fifth input terminal (e) is connected to one input of a second XOR gate (30) and to one input of a second NAND gate (32). The first XOR gate (22) has its output connected to the other input of the first NAND gate (28) and to the control input of the multiplexor (24). The output of the multiplexor (24) is connected to the other inputs of the second XOR gate (30) and second NAND gate (32). The outputs of the first and second NAND gates (28, 32) are connected to the inputs of a third NAND gate (36). The outputs of the third NAND gate (36) and second XOR gate (30) are the output terminals (F2, F1) of the logic module (10). The configuration of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.