Local and express diagonal busses in a configurable logic array
US5338984A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 5, 1993 |
| Grant date | Aug 16, 1994 |
| Priority date | — |
| Expiry date | Feb 5, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical columns of logic cells. The array further includes at least one horizontally aligned express bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned express bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array further includes at least one generally diagonally aligned local and/or express bus running between adjacent diagonally aligned logic cells, the adjacent diagonally aligned logic cells being connectable thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.