Arrangement for monitoring the bit rate in ATM networks
US5339332A · kind A · utility
34Cited by
7References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 20, 1992 |
| Grant date | Aug 16, 1994 |
| Priority date | — |
| Expiry date | Aug 20, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5637
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
For a dual leaky bucket ATM bit rate monitoring wherein the peak bit rate is monitored in a first leaky bucket unit and the maximum cell plurality of a full rate burst is declared, the duration of peak rate bursts is monitored in a second leaky bucket unit with a first counter respectively reset to 0 when the counter reading returns below a defined value. The average bit rate is monitored with a second counter having a lower response threshold, and which is incremented only with a smoothed cell rate given higher bit rates,
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.