Interconnection network and crossbar switch for the same
US5339396A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1993 |
| Grant date | Aug 16, 1994 |
| Priority date | — |
| Expiry date | Sep 10, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17381
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a parallel computer including L=n.sub.1 x n.sub.2 x - - - x n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L x (1/n.sub.1 +1/n.sub.2 +- - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N) , 0.ltoreq.i.sub.1 .ltoreq.n.sub.1-1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2-1, - - - , 0.ltoreq.i.sub.n .ltoreq.n.sub.N-1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e., having processor element numbers ##EQU1## by using one of the crossbar switches, each of the crossbar switches having n.sub.k inputs and n.sub.k outputs, and the interconnection performed with respect to all (L/n.sub.k sets) of coor…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.