Cache controller that alternately selects for presentation to a tag RAM a current address latch and a next address latch which hold addresses captured on an input bus
US5339399A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1991 |
| Grant date | Aug 16, 1994 |
| Priority date | — |
| Expiry date | Apr 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache controller sits in parallel with a microprocessor bus and includes a tag RAM for associatively searching a directory for cache data-array addresses. Two normal address latches are provided to capture a cycle address in case the current cycle is extended by a pending tag RAM access. At any time, except when the next cycle has started, but during which the current cycle is in progress, one latch is open to an input buffer such that the input address is latched by that latch. The other latch holds the current cycle address until the cycle ends. The current cycle can be extended with snoops. The current cycle address has to be maintained as long as the cycle is still in progress. In the meantime, the external cycle might have ended and a next cycle started. The second address latch is used to capture the address corresponding to this new cycle. As signal selects which of the two latches will supply the address via a MUX to the tag RAM. Logic switches the two input address latches so that the tag RAM sees a constant address for the duration of a cycle while at the same time a new cycle address can be received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.